Semiconductor device and manufacturing method of the same

ABSTRACT

The present invention intends to provide a technique that can improve the capacitance density while securing the withstand voltage of a capacitor element. In order to achieve the above object, the present inventive manufacturing method of a semiconductor device includes forming a metal film on a silicon oxide film, forming a SiN film on the metal film, forming a metal film on the SiN film, etching the upper most metal film with a photoresist film as a mask to form an upper electrode, thereafter forming a silicon oxide film that covers the upper electrode, patterning by etching the silicon oxide film and the SiN film with a photoresist film as a mask to form a capacitor insulating film and sputter-etching the lowermost metal film with the patterned silicon oxide film as a mask to form a lower electrode.

CROSS REFERENCES

This is a divisional application of U.S. Ser. No. 11/007,340, filed Dec.10, 2004 (now allowed).

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and amanufacturing method of the same. In particular, the present inventionrelates to a technique effective in applying in a formation process of acapacitor element that is formed integrated with a transistor and aresistance element on a substrate.

2. Description of the Related Art

For instance, in patent literatures 1, 2, 3 and 4, a technique in whichan HBT (Hetero-junction Bipolar Transistor), a resistance element and acapacitor element are formed on the same substrate is disclosed.

Patent literature 1: JP-A No. 2001-77204

Patent literature 2: JP-A No. 2001-326284

Patent literature 3: JP-A No. 2001-156179 and

Patent literature 4: JP-A No. 2002-252344

An HBT is considered being studied for use in a high-output poweramplifier as a high-output power device capable of operating under asingle power supply. In addition, since the HBT has the characteristicsof being capable of being operated with high efficiency, etc., atechnique for applying in a mobile communication device such as aportable telephone is under consideration. In the case of the HBT beingapplied to the mobile communication device, not only making theperformance of the HBT element higher, but also miniaturizing asemiconductor chip (hereinafter simply referred to as chip) on which theHBT is formed, and forming a passive element such as a resistanceelement or a capacitor element and the HBT in the same chip aredemanded.

The present inventors are studying an HBT that is used in ahigh-frequency module contained in a mobile communication device andalso studying a technique of forming the HBT together with passiveelements such as a resistance element and a capacitor element in onechip. In the course, the inventors found problems mentioned below. Theseproblems will be explained with reference to FIGS. 39 and 40.

FIG. 39 is an essential sectional view of one example of a chip that theinventors have studied. Although in the chip, an HBT and passiveelements such as a resistance element and a capacitor element areformed, in FIG. 39 a cross section of a capacitor element isillustrated. A process that forms a capacitor element in a chip and wasstudied by the inventors is as follows. On an insulating film 102 thatis deposited on a semi-insulating substrate (hereinafter simply referredto as a substrate) 101 that has, for instance, GaAs (gallium arsenide)as a main component, a metal film 103 is formed and the metal film 103is patterned. Subsequently, after on the substrate 101, an interlayerinsulating film 104 that covers the metal film 103 is deposited, anopening 105 that reaches the metal film 103 is formed in the interlayerinsulating film 104. In the next place, after an insulating film 106 isdeposited on the interlayer insulating film 104 including the inside ofthe opening 105 thereof, the insulating film 106 is patterned.Subsequently, after a metal film 107 is deposited on the substrate 101,the metal film 107 is patterned. Thereby, a capacitor element C11 isformed in which the metal film 103 is a lower electrode, the insulatingfilm 106 is a capacitor insulating film and the metal film 107 is anupper electrode. The inventors found that when a capacitor element C11is formed according to such a process, the insulating film 106 bends ina lower region 105A of a sidewall of the opening 105 and a filmthickness becomes thinner than other regions or film quality isdeteriorated. When the film thickness of the insulating film 106 becomesthinner, the withstand voltage of the capacitor element C11 isdeteriorated in the lower region 105A; accordingly, there is a problemin that a measure of improving a capacitance density of the capacitorelement C11 by thinning a film thickness of the insulating film 106cannot be taken. Furthermore, depending on the deposition conditions ofan insulating film, an insulating film can be formed without reducing afilm thickness in the lower region 105A. However, even in such cases,often times deterioration of film quality is caused. That is, owing tothe deterioration of the film quality, a phenomenon that the withstandvoltage at the region 105A deteriorates to not more than half of thewithstand voltage at a planar portion is likely to occur. This isbecause although a plasma CVD (Chemical Vapor Deposition) device or thelike is used to form an insulating film, the film quality and a filmthickness at a stepped portion can be controlled with more difficulty incomparison with that in a planar portion. Furthermore, when thecapacitor element C11 is formed, a process of forming the opening 105and a process of patterning the insulating film 106 are necessary.Accordingly, there is another problem in that the number of processesfor manufacturing a chip increases.

FIG. 40 is an essential sectional view of another example of a chip thatthe inventors studied. Also, in a chip shown in FIG. 40, similarly tothe chip shown in FIG. 39, an HBT and passive elements such as aresistance element and a capacitor element are formed. However, in FIG.40, a sectional view of a capacitor element is illustrated. A processthat forms a capacitor element in the chip and was studied by theinventors is same as that for the chip explained with FIG. 39 up to aprocess of patterning the metal film 103. Thereafter, an insulating film106 is deposited on a substrate 101. Subsequently, after a metal film107 is deposited on the insulating film 106, the metal film 107 ispatterned. Thereby, a capacitor element C11 is formed in which the metalfilm 103 is a lower electrode, the insulating film 106 is a capacitorinsulating film and the metal film 107 is an upper electrode. In theexample shown in FIG. 40, the insulating film 106 combines with an interlayer insulating film as well. The inventors found that when a capacitorelement C11 is formed according to a process like this, in a region 103Aof a sidewall lower portion of the metal film 103, a sidewall portionand a region up to a region 103B of a sidewall upper portion, a filmthickness of the insulating film 106 becomes thinner than other regionsor film quality is likely to deteriorate. Thus, when, in depositing theinsulating film 106, the insulating film 106 becomes partially thinneror the film quality deteriorates, similarly to an example shown in FIG.37, there is a problem in that a measure of improving the capacitancedensity of the capacitor C11 by thinning a film thickness of theinsulating film 106 can be taken with difficulty.

An object of the present invention is to provide a technology that canimprove the capacitance density while securing the withstand voltage ofa capacitor element.

The above-mentioned and other objects and novel characteristicsaccording to the present invention will be clarified from descriptionsin the present specification and attached drawings.

SUMMARY OF THE INVENTION

Among inventions that will be disclosed in the present application,representative outlines are briefly explained as follows.

A semiconductor device according to the present invention includes acapacitor element that is formed on a substrate made of a semiconductorsubstrate or an insulator substrate; the capacitor element having alower electrode formed on the substrate, a capacitor insulating filmformed on the lower electrode and an upper electrode formed on thecapacitor insulating film; the lower electrode, the capacitor insulatingfilm and the upper electrode being formed flat on the substrate; and ina plane an outer periphery of the upper electrode being disposed moreinside than an outer periphery of the lower electrode.

Furthermore, a manufacturing method according to the present inventionof a semiconductor device includes (a) sequentially depositing on asubstrate made of a semiconductor substrate or an insulator substrate afirst conductive film, a first insulating film and a second conductivefilm,

(b) patterning the second conductive film to form an upper electrode,and (c) after the step (b), patterning the first conductive film to forma lower electrode and thereby forming a capacitor element including theupper electrode, the capacitor insulating film and the lower electrode.

Among inventions that will be disclosed in the present application, aneffect that is obtained according to typical one is briefly described asfollows.

That is, with securing the withstand voltage of a capacitor element thecapacitance density can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an essential sectional view for explaining a manufacturingmethod of a semiconductor device that is embodiment 1 according to thepresent invention.

FIG. 2 is subsequent to FIG. 1 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 3 is subsequent to FIG. 2 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 4 is subsequent to FIG. 3 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 5 is an essential sectional view in the process of manufacture of asemiconductor device that is embodiment 1 according to the invention.

FIG. 6 is an essential sectional view in the process of manufacture of asemiconductor device that is embodiment 1 according to the invention.

FIG. 7 is subsequent to FIG. 4 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 8 is subsequent to FIG. 7 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 9 is an essential plan view in the process of manufacture of asemiconductor device that is embodiment 1 according to the invention.

FIG. 10 is subsequent to FIG. 8 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 11 is subsequent to FIG. 9 and an essential plan view in theprocess of manufacture of a semiconductor device.

FIG. 12 is an essential sectional view in the process of manufacture ofa semiconductor device that is embodiment 1 according to the invention.

FIG. 13 is subsequent to FIG. 10 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 14 is an essential sectional view for explaining a manufacturingmethod of a semiconductor device that is embodiment 2 according to theinvention.

FIG. 15 is subsequent to FIG. 14 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 16 is subsequent to FIG. 15 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 17 is subsequent to FIG. 16 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 18 is subsequent to FIG. 17 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 19 is an essential sectional view for explaining a manufacturingmethod of a semiconductor device that is embodiment 3 according to theinvention.

FIG. 20 is subsequent to FIG. 19 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 21 is subsequent to FIG. 20 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 22 is subsequent to FIG. 21 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 23 is subsequent to FIG. 22 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 24 is subsequent to FIG. 23 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 25 is subsequent to FIG. 24 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 26 is subsequent to FIG. 25 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 27 is subsequent to FIG. 26 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 28 is subsequent to FIG. 27 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 29 is an essential plan view in the process of manufacture of asemiconductor device that is embodiment 3 according to the invention.

FIG. 30 is subsequent to FIG. 28 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 31 is subsequent to FIG. 29 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 32 is subsequent to FIG. 30 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 33 is subsequent to FIG. 31 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 34 is subsequent to FIG. 32 and an essential sectional view in theprocess of manufacture of a semiconductor device.

FIG. 35 is a plan view of a chip that forms a semiconductor device thatis embodiment 3 according to the invention.

FIG. 36 is an essential plan view of a high-frequency power amplifierincluding a chip shown in FIG. 35.

FIG. 37 is an essential circuit diagram of a high-frequency poweramplifier shown in FIG. 36.

FIG. 38 is an essential sectional view for explaining a semiconductordevice that is embodiment 3 according to the invention.

FIG. 39 is an essential sectional view of a semiconductor device thatinventors have studied.

FIG. 40 is an essential sectional view of a semiconductor device thatinventors have studied.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In what follows, embodiments according to the present invention will bedetailed based on the drawings. In all drawings for explaining theembodiments, as a general rule, to identical members, identicalreference numerals are given and repetition of explanation thereof willbe omitted.

Embodiment 1

In a semiconductor device according to embodiment 1, for instance, a FET(Field Effect Transistor), a resistance element and a capacitor elementare integrally formed on a substrate. A manufacturing process of thesemiconductor device according to the embodiment 1 will be explainedalong a manufacturing process with reference to FIGS. 1 through 13.

Firstly, as shown in FIG. 1, a semi-insulating GaAs substrate 1 havingthe resistivity of substantially 1×10⁻⁷ Ω·cm is prepared. Subsequently,for instance, by means of a metal organic chemical vapor deposition(MOCVD) method, on the GaAs substrate 1, an n-type GaAs layer 2 dopedwith an impurity (such as Si (silicon)) having the n-type conductivityis grown. Subsequently, the n-type GaAs layer 2 in a region other thanthat where an FET is formed according to a mesa etching method is etchedto form an element isolation portion 3. Subsequently, with a photoresistfilm patterned according to the photolithography technique as a mask, onthe n-type GaAs layer 2 in a region where the FET is formed, a AuGe(gold germanium) film, a Ni (nickel) film and a Au (gold) film aresequentially deposited, thereby a source electrode 4 and a drainelectrode 5 that form ohmic-contact with the n-type GaAs layer 2 areformed. Then, after the photoresist film that is used to form the sourceelectrode 4 and the drain electrode 5 is removed, with a photoresistfilm newly patterned according to the photolithography technique as amask, on the n-type GaAs layer 2 in a region where the FET is formed, alaminated layer containing Pt (platinum) and Au is deposited, thereby agate electrode 6 that forms Schottky contact with the n-type GaAs layer2 is formed. According to a process until here, a MESFET (MetalSemiconductor Field Effect Transistor) can be formed. After theformation of the gate electrode 6, the photoresist film is removed.

In the next place, as shown in FIG. 2, according to, for instance, a CVDmethod, a silicon oxide film 7 having a film thickness of substantially500 nm is deposited on the GaAs substrate 1. Subsequently, after on thesilicon oxide film 7 a WSiN (tungsten nitride silicide) film isdeposited, with a photoresist film patterned by means of thephotolithography technique as a mask, the WSiN film is etched to form aresistance element 9. After the formation of the resistance element 9,the photoresist film is removed. In the present embodiment 1, a casewhere the resistance element 9 is formed from a WSiN film isillustrated; however, it may be formed from, in place of the WSiN film,a NiCr (nickel chrome) film.

In the next place, as shown in FIG. 3, for instance, a silicon oxidefilm 10 is deposited on the GaAs substrate 1. Subsequently, with aphotoresist film patterned by means of the photolithography technique asa mask, silicon oxide films 7 and 10 are etched, and thereby an opening11 that reaches the source electrode 4, an opening 12 that reaches agate electrode 6, an opening 13 that reaches the drain electrode 5 andan opening 14 that reaches the resistance element 9 are formed.

In the next place, as shown in FIG. 4, a metal film (first conductivefilm) 15 that buries the openings 11 through 14 is deposited on thesilicon oxide film 10. As shown in FIG. 15, the metal film 15 can beformed by sequentially depositing a Mo (molybdenum) film (first metalfilm) 15A having a film thickness of substantially 0.1 μm, a Au (gold)film (second metal film) 15B having a film thickness of substantially0.8 μm and a Mo film (third metal film) 15C having a film thickness ofsubstantially 0.1 μm. Furthermore, on an upper portion of the Mo film15C that is the uppermost layer of the metal film 15, a TiW (titaniumtungsten) film may be further laminated. Alternatively, instead of usingthe Mo film 15A and the Mo film 15C, a Ti (titanium) film, a W(tungsten) film, a TiW film or a WSi (tungsten silicide) film may beused. Subsequently, for instance, on the metal film 15, according to theplasma CVD method, a SiN (silicon nitride) film (first insulating film)16 having a film thickness of substantially 100 nm is deposited.subsequently, on the SiN film 16, a metal film (second conductive film)having a film thickness of substantially 200 nm is deposited. In theembodiment 1, as the metal film, a TiW film or a WSi film can beillustrated. Subsequently, with a photoresist film patterned by means ofthe photolithography technique as a mask, the metal film is etched, andthereby an upper electrode 17 of a capacitor element that is formed in alater process is formed. When the upper electrode 17 is formed by meansof etching, for instance the dry etching is used. Normally, in the dryetching, the etching is difficult to confine to the processing of theupper electrode 17, thereby, the SiN film 16 as an underlayer, ispartially trimmed. This is because in order to completely etch the metalfilm other than the upper electrode 17, in considering the dispersion inthe process owing to a dry etching machine, so-called over-etching iscarried out. Furthermore, in some cases, as shown in FIG. 6, theunderlying SiN film 16 (first insulating film) may be completely groundor the Mo film 15C further there below may be partially ground. In thiscase, different from a shape shown in a later described FIG. 7, acapacitor insulating film of a capacitor element is planar and formed ina shape substantially same as the upper electrode. Furthermore, otherthan the dry etching method, by means of a lift-off method due to aphotoresist mask, the upper electrode 17 such as Mo may be patterned. Inthis case, the SiN film 16, without being ground, becomes a crosssection same as that shown in FIG. 4.

In the next place, as shown in FIG. 7, on the GaAs substrate 1 a siliconoxide film 18 having a film thickness of substantially 0.8 μm isdeposited, and the silicon oxide film (second insulating film) 18 coversthe upper electrode 17. In place of the silicon oxide film 18, a SiNfilm may be used. Subsequently, owing to the etching with a photoresistfilm patterned by use of the photolithography technique as a mask, thesilicon oxide film 18 and the SiN film 16 are patterned. At this time,the Mo film 15C at the uppermost layer of the metal film 15 may bepatterned as well. Thereby, a capacitor insulating film 16A of acapacitor element that is formed from the SiN film 16 in a later processcan be formed. After the capacitor insulating film 16A is formed, thephotoresist film used to form the capacitor insulating film 16A isremoved.

In the next place, as shown in FIG. 8, with the silicon oxide film 18 asa mask, the sputter etching is applied with an Ar ion to pattern themetal film 15. Thereby, from the metal film 15, a lower electrode 15D ofthe capacitor element, a wiring 15E electrically connecting with thesource electrode 4, a wiring 15F electrically connecting with the gateelectrode 6, a wiring 15G electrically connecting with the drainelectrode 5 and a wiring 15H electrically connecting with the resistanceelement 9 can be formed. According to the process until here, acapacitor element C made of the lower electrode 15D, the capacitorinsulating film 16A and the upper electrode 17 can be formed. Here, FIG.9 is a plan view of the capacitor element C and a cross section along anA-A line in FIG. 9 corresponds to a cross section of the capacitorelement C in FIG. 8. In the embodiment 1, as shown in FIG. 9, the lowerelectrode 15D (the capacitor insulating film 16A) is patterned so as tosurround the upper electrode 17. At this time, the metal film 15 ispatterned by means of the sputter etching. This is because Au that formsthe metal film 15 is a material that is difficult to etch according to achemical reaction. Furthermore, since the metal film 15 is physicallyetched (sputter etching) to pattern, Au and Mo that form the metal film15 that is ground by means of the sputter etching are splattered.However, since at the time of patterning the metal film 15 the upperelectrode 17 is covered with the silicon oxide film 18, the Au and Mocan be inhibited from inconveniently adhering to the upper electrode 17.Thereby, the upper electrode 17 and the lower electrode 15D can beinhibited from inconveniently causing an electrical short circuit.

In forming the capacitor element, for instance in the case that a lowerelectrode and a wiring are patterned beforehand, on the lower electrodean interlayer insulating film is formed, and in the interlayerinsulating film an opening that reaches the lower electrode is formed,then a capacitor insulating film and an upper electrode being formed inthe opening, in particular at the lowermost portion of a sidewall of theopening, the capacitor insulating film bends, a film thickness of thecapacitor insulating film becomes thinner or the film qualitydeteriorates; accordingly, there is fear in that the withstand voltageof the capacitor element may be deteriorated. According to experimentscarried out by the inventors, in the case of a capacitor insulating filmbeing deposited with a film thickness of substantially 100 nm, in manycases, the breakdown withstand voltage, which is expected to besubstantially 80 to 100 V, becomes substantially 50 V or less.Accordingly, there is fear in that by thinning a film thickness of acapacitor insulating film the capacitance density of the capacitorelement may become difficult to improve. On the other hand, according toa method of forming a capacitor element according to the embodiment 1,since, without forming such an opening, the metal film 15 (FIG. 4) thatbecomes the lower electrode 15D, the SiN film 16 that becomes thecapacitor insulating film 16A and the metal film that becomes the upperelectrode 17 are successively deposited, the capacitor insulating filmcan be inhibited from becoming locally thinner. Furthermore, asexplained with FIG. 9, since the lower electrode 15D (capacitorinsulating film 16A) is planar and patterned so as to surround the upperelectrode 17, below the upper electrode 17, the capacitor insulatingfilm 16A can be inhibited from being disposed at an upper portion of asidewall and at a lower portion of the sidewall of the lower electrode15D. That is, in the capacitor element C, the withstand voltage of thecapacitor element C can be inhibited from deteriorating because thecapacitor insulating film 16A bends, the capacitor insulating film 16Abecomes locally thinner in a film thickness or the film quality isdeteriorated. Thereby, the breakdown withstand voltage of the capacitorelement C can be improved. As a result, according to the embodiment 1,by thinning a film thickness of a capacitor insulating film, thecapacitance density of the capacitor element can be improved. Accordingto experiments carried out by the inventors, it was found that while inthe case of the opening being disposed to form a capacitor element afilm thickness of the capacitor insulating film was set at substantially150 nm, in the case of a capacitor element C according to the embodiment1 a film thickness of a capacitor insulating film can be set atsubstantially 100 nm, resulting in an improvement of substantially 1.5times in the capacitance density. That is, according to the embodiment1, when a capacitor element C same in the capacitance value as that of acapacitor element formed by disposing an opening is formed, an area thatthe capacitor element C occupies can be reduced to substantially twothirds.

Furthermore, according to a method of forming a capacitor element Caccording to the embodiment 1, the metal film 15 that becomes a lowerelectrode 15D, the SiN film 16 that becomes a capacitor insulating film16A and the metal film that becomes an upper electrode 17 aresuccessively deposited; accordingly, density of impurities that enterbetween the lower electrode 15D and the upper electrode 17 can bereduced. Thereby, the capacitance withstand voltage can be inhibitedfrom deteriorating owing to defects caused by the impurities.

In the next place, as shown in FIG. 10, on the GaAs substrate 1 a SiNfilm having a film thickness of substantially 0.5 μm and a silicon oxidefilm having a film thickness of substantially 0.5 μm are successivelydeposited to form an insulating film (third insulating film) 19.Subsequently, with a photoresist film patterned according to thephotolithography technique as a mask, the insulating film 19 is etched,and thereby an opening 20 that reaches each of wirings 15E through 15H,an opening (second opening) 21 that reaches a lower electrode 15D in aregion that is planar and where the upper electrode 17 is not disposedand an opening (first opening) 22 that reaches the upper electrode 17are simultaneously formed. At this time, an opening area of the opening22 is formed so as to be larger that an opening area of the opening 21.Subsequently, on the insulating film 19 including the insides of theopenings 20 through 22, a Mo film having a film thickness ofsubstantially 0.2 μm and a Au film having a film thickness ofsubstantially 3 μmare sequentially deposited. Then, according to theetching with a photoresist film patterned according to thephotolithography technique as a mask, the Au film and Mo film arepatterned to form a wiring 23 that electrically comes into contact witheach of the wirings 15E through 15H, a wiring (second wiring) 24 thatelectrically comes into contact with the lower electrode 15D and awiring (first wiring) 25 that electrically comes into contact with theupper electrode. Here, FIG. 11 is a plan view of the capacitor element Cin the formation of the wirings 23, 24 and 25 and a cross section alongan A-A line in FIG. 11 corresponds to a cross section of the capacitorelement C in FIG. 10. As shown in FIG. 11, the opening 22 is formed soas to be planar and surrounded by the upper electrode 17. When theopening 22 is planar and formed at a position deviated from the upperelectrode 17, there is fear in that owing to the wiring 25 disposedinside of the opening 22, the upper electrode 17 and lower electrode 15Dmay be caused to short-circuit. However, when the opening 22 is formedplanar and so as to be surrounded with the upper electrode 17, suchinconveniences can be inhibited from occurring.

In the case of a capacitor element being formed according to a processwhere, as described in the explanation of FIG. 39, after a lowerelectrode and a wiring are patterned beforehand, an interlayerinsulating film is formed on the lower electrode and an opening 105 thatreaches the lower electrode is formed in the interlayer insulating film,a capacitor insulating film and an upper electrode are formed in theopening to form a capacitor element, it becomes difficult to form anopening in which the capacitor insulating film is formed and the openingF that electrically connects in other regions a lower electrode or awiring in the same layer as the lower electrode in the same process.Here, the opening F corresponds to the opening 20 in the above example.When the opening F and the opening 105 (FIG. 39) of a capacitor portionare tentatively formed simultaneously, since after that the capacitorinsulating film is deposited, the capacitor insulating film is depositedalso in the opening F. As a result, owing to the capacitor insulatingfilm deposited in the opening, the lower electrode or the wiring in alayer same as the lower electrode and a wiring in a layer thereabovebecome incapable of electrically connecting. In order to inhibit suchinconveniences from occurring, above two openings are demanded to formin separate processes. Alternatively, as a separate idea, a method inwhich an opening 105 alone is formed beforehand, a capacitor insulatingfilm is formed over an entire surface, and, without patterning thecapacitor insulating film, an opening F for electrically connecting alower electrode or a wiring in a layer same as the lower electrode isformed is considered. In the method, when the opening F is formed, twodifferent layers of the capacitor insulating film and the interlayerinsulating film are etched. In the case of the two different layers ofthe capacitor insulating film and the interlayer insulating film beingetched in a lump to form an opening, a shape of the opening to be formedis controlled with difficulty; accordingly, this method is alsodifficult to apply. Resultantly, it is demanded to etch the capacitorinsulating film and the interlayer insulating film in separateprocesses. That is, an opening for forming a wiring that electricallyconnects with a lower electrode is demanded to form in two processes. Onthe other hand, according to the embodiment 1, an opening 21 for forminga wiring 24 that electrically connects with a lower electrode 15D and anopening 20 that reaches each of wirings 15E through 15H can be formed ina process same as that that forms an opening 22 that reaches an upperelectrode 17; accordingly, a manufacturing process of a semiconductordevice can be simplified. The opening 21 and the wiring 24 forelectrically connecting with the lower electrode 15D may be omitteddepending on circumstances. For instance, as shown in FIG. 12, the lowerelectrode 15D may be directly connected to a wiring 15 that connects theresistance element 9 or a wiring 15G of a drain portion.

Furthermore, though omitted from showing in the drawing, a Au film and aMo film that form wirings 23, 24 and 25 may be patterned in a planarspiral to form an inductor.

In the next place, as shown in FIG. 13, on the GaAs substrate 1, forinstance a polyimide resin film is coated and thereby a protective film26 is formed. Thereafter, the GaAs substrate 1 is cut by means of adicing method or the like into individual chips to form a semiconductordevice according to embodiment 1.

Embodiment 2

In a semiconductor device according to present embodiment 2, similarlyto the embodiment 1, a FET, a resistance element and a capacitor elementare integrated on a substrate. A manufacturing method of thesemiconductor device according to the embodiment 2 will be explainedwith reference to FIGS. 14 through 18.

A manufacturing process of the semiconductor device according to theembodiment 2 is similar up to a process of forming an element isolationlayer 3 (FIG. 1) in the embodiment 1. Thereafter, a metal film 15I madeof, for instance, a WSi (tungsten silicide) film, a SiN film 16 same asthe SiN film 16 in the embodiment 1, and a metal film same as the metalfilm laminated on the SiN film 16 in the embodiment 1 are successivelydeposited on a GaAs substrate 1. Subsequently, with a photoresist filmpatterned according to the photolithography technique as a mask, themetal film is etched, and thereby an upper electrode 17 of a capacitorelement that is formed in a later process is formed. After the upperelectrode 17 is formed, the photoresist film is removed. A planarpattern of the upper electrode 17 is same as a pattern explained withFIG. 9 in the embodiment 1.

In the next place, as shown in FIG. 15, by means of the dry etchingwhere a photoresist film patterned according to the photolithographytechnique is used as a mask, the SiN film 16 and the metal film 15I arepatterned. Thereby, from the SiN film 16 a capacitor insulating film 16Aof a capacitor element can be formed and from the metal film 15I a gateelectrode 6A and a lower electrode 15J of the capacitor element can beformed. When the metal film 15I is dry-etched, as an etching gas, forinstance, a SF₆ gas can be used. Furthermore, planar patterns of thecapacitor insulating film 16A and the lower electrode 15J are same asthe patterns explained with FIG. 9 in the embodiment 1. According to theprocess up to here, a capacitor element C1 constituted of the lowerelectrode 15J, the capacitor insulating film 16A and the upper electrode17 can be formed. According to the embodiment 2 like this, since thegate electrode 6A and the lower electrode 15J of the capacitor elementC1 can be formed in the same process, a manufacturing process of asemiconductor device can be more simplified than the embodiment 1.Furthermore, in the embodiment 1, since the metal film 15 that becamethe lower electrode 15D (FIG. 8) of the capacitor element C contained achemically stable Au film 15B (FIG. 7), a physical etching method(sputtering etching) was used to etch the metal film 15. However, in theembodiment 2, the metal film 15I is formed of a WSi film; accordingly,the metal film 15I can be patterned according to the dry etching. In theembodiment 1, a case where the lower electrode 15J and the gateelectrode 6A are formed in the same process was explained; however,these may be formed according to separate processes.

Next, as shown in FIG. 16, with a photoresist film patterned accordingto the photolithography technique as a mask, on an n-type GaAs layer 2in a region where an FET is formed a AuGe (gold germanium) film, a Ni(nickel) film and a Au film are sequentially deposited to form a sourceelectrode 4 and a drain electrode 5 that come into ohmic contact withthe n-type GaAs layer 2 same as the embodiment 1. According to a processup to here, a MESFET can be formed. After the source electrode 4 and thedrain electrode 5 are formed, the photoresist film is removed.

In the next place, as shown in FIG. 17, on the GaAs substrate 1, asilicon oxide film 7 same as the silicon oxide film 7 in the embodiment1 is deposited. Subsequently, after WSiN is deposited on the siliconoxide film 7, with a photoresist film patterned by means of thephotolithography technique as a mask, the WSiN film is etched, andthereby a resistance element 9 same as the resistance element 9 in theembodiment 1 is formed.

Subsequently, as shown in FIG. 18, on the GaAs substrate 1, aninsulating film 19 same as the insulating film 19 in the embodiment 1 isformed. Subsequently, the insulating film 19 is etched with aphotoresist film patterned by means of the photolithography technique asa mask, thereby an opening 20A that reaches each of the source electrode4, a gate electrode 6A and the drain electrode 5, an opening 20B thatreaches a resistance element 9 and openings 21 and 22 same as theopenings 21 and 22 in the embodiment 1 are formed. Still subsequently,on the insulating film 19 including the insides of the openings 20A,20B, 21 and 22, a Mo film having a film thickness of substantially 0.2μm and a Au film having a film thickness of substantially 3 μm aresequentially formed. Subsequently, by etching with a photoresist filmpatterned by means of the photolithography technique as a mask, the Aufilm and the Mo film are patterned to form a wiring 23A thatelectrically connects with each of the source electrode 4, the gateelectrode 6A and the drain electrode 5, a wiring 23B that electricallyconnects with the resistance element 9, a wiring 24 that electricallyconnects with the lower electrode 15J and a wiring 25 that electricallyconnects with the upper electrode. Thereafter, on the GaAs substrate 1,a protective film 26 same as the protective film 26 in the embodiment 1is formed, thereby a semiconductor device according to the embodiment 2is manufactured.

The opening 21 and the wiring 24 for electrically connecting with thelower electrode 15J may be omitted in some cases. For instance, the gateelectrode 6A is extended and may be directly connected with the lowerelectrode 15J. In this case, since the opening 21 can be done without, alayout area can be reduced.

Even according to the embodiment 2 as mentioned above, an effect same asthe embodiment 1 can be obtained.

Embodiment 3

A semiconductor device according to embodiment 3 is one formed byintegrating an HBT, a resistance element and a capacitor element on asubstrate. A manufacturing process of the semiconductor device accordingto the embodiment 3 will be explained.

Firstly, as shown in FIG. 19, a semi-insulating GaAs substrate 1 havingthe resistivity of substantially 1×10⁻⁷ Ω·cm is prepared. Subsequently,according to the MOCVD method, substantially 700 nm of an n⁺ type (firstconductivity type) GaAs layer 32 that becomes a sub-collector layer isgrown. Subsequently, on the n⁺ type GaAs layer 32, an n⁻ type GaAs layer33 that becomes a collector layer and a p⁺ type (second conductivitytype) GaAs layer 34 that becomes a base layer are successively formedaccording to the MOCVD method.

In the next place, an n-type InGaP layer 35 that becomes an emitterlayer is deposited according to the MOCVD method, further thereonsubstantially 400 nm of an n⁺-type InGaAs layer 36 that becomes anemitter contact layer is formed. The n⁺-type InGaAs layer 36 is used toestablish an ohmic contact with an emitter electrode that is formed in alater process. Thus, for a base (p⁺ type GaAs layer 34) and an emitterlayer (n-type InGaP layer 35), different kinds of semiconductors(hetero-junction) are used.

Subsequently, as a conductive film, for instance, substantially 300 nmof a WSi film is deposited according to the sputtering method.Subsequently, by use of the photolithography technique and thedry-etching technique, the WSi film is processed to form an emitterelectrode 37.

In the next place, as shown in FIG. 20, with the emitter electrode 37 asa mask, the emitter contact layer (n⁺-type InGaAs layer 36) iswet-etched to expose the emitter layer (n-type InGaP layer 35). At thistime, the emitter layer (n-type InGaP layer 35) may be etched to exposethe base layer (p⁺ type GaAs layer 34).

Subsequently, a base electrode 38 made of a laminated base film in whichPt, Ti (titanium), Mo, Ti and Au are laminated from bottom up is formed.The base electrode 38 is formed according to, for instance, a lift-offmethod and a thickness thereof is substantially 300 nm. Thereafter, byapplying heat treatment (alloying treatment), Pt at the lowermost layerof the base electrode 38 is allowed to react with the emitter layer(n-type InGaP layer 35) and the base layer (p⁺ type GaAs layer 34).Owing to the reaction portion, the ohmic contact of the base electrode38 and the base layer (p⁺ type GaAs layer 34) can be obtained.

Still subsequently, by use of the photolithography technique and the wetetching technique, the emitter layer (n-type InGaP layer 35) and thebase layer (p⁺ type GaAs layer 34) are etched to form a base mesa 34A.As an etching liquid, for instance, a mixed aqueous solution ofphosphoric acid and hydrogen peroxide is used. Owing to the etching, theemitter layer (n-type InGaP layer 35) and the base mesa 34A areseparated for each of transistors.

In the next place, as shown in FIG. 21, substantially 100 nm of aninsulating film (such as silicon oxide film) 39 is deposited on the GaAssubstrate 1. The insulating film 39, though formed to protect the baseelectrode 38, may be omitted. Subsequently, the insulating film 39 andthe collector layer (n type GaAs layer 33) are selectively etched toform an opening (first region) 40 that reaches a sub-collector layer (n⁺type GaAs layer 32).

In the next place, as shown in FIG. 22, with a photoresist film (omittedfrom showing in the drawing) patterned according to the photolithographytechnique as a mask, on an entire surface of the GaAs substrate 1, AuGe,Ni and Au are sequentially formed from bottom up, and on an upperportion of the photoresist film and the exposed sub-collector layer (n⁺type GaAs layer 32) a laminated film is formed. Subsequently, thephotoresist film is removed with a peeling liquid (etching liquid). Whenthe photoresist film is removed thus, the laminated film thereabove isalso peeled and the laminated film remains only on part of thesub-collector layer (n⁺ type GaAs layer 32) to form a collectorelectrode 41. According to the process up to here, an npn-type HBTaccording to the embodiment 3 can be formed.

In the next place, as shown in FIG. 23, the insulating film 39 isremoved, the collector layer (n⁻ type GaAs layer 33) and thesub-collector layer (n⁺ type GaAs layer 32) outside of the collectorelectrode 41 are etched to form an element isolation region 42, andthereby the respective HBTs are electrically isolated.

In the next place, as shown in FIG. 24, on the GaAs substrate 1, aninsulating film (such as silicon oxide film) 43 is deposited by means ofthe CVD method. With the insulating film 39 (FIG. 22) remained, thecollector layer (n⁻ type GaAs layer 33) and the sub-collector layer (n⁺type GaAs layer 32) are etched to electrically separate the respectiveHBTs, thereby the insulating film 43 may be formed on the insulatingfilm 39.

Subsequently, after WSiN is deposited on, for instance, the insulatingfilm 43, with a photoresist film patterned according to thephotolithography technique as a mask, the WSiN film is etched to form aresistance element 44. In the embodiment 3, a case where the resistanceelement 44 is formed from a WSiN film is shown. However, in place of theWSiN film, it may be formed from a NiCr film.

In the next place, as shown in FIG. 25, on the GaAs substrate 1, aninsulating film 45 (such as silicon oxide film) is deposited.Subsequently, with a photoresist film patterned according to thephotolithography technique as a mask, the insulating films 45 and 43 areetched and thereby an opening (omitted from showing in the drawing) thatreaches the emitter electrode 37, an opening 46 that reaches the baseelectrode 38, an opening 47 that reaches the collector electrode 41 andan opening 48 that reaches the resistance element 44 are formed.

In the next place, as shown in FIG. 26, on the insulating film 45, ametal film 49 that buries the openings 46 through 48 (FIG. 25) and has afilm thickness of substantially 1 μm, an insulating film 50 having afilm thickness of substantially 100 nm, a metal film 51 having a filmthickness of substantially 1 μm, an insulating film 52 having a filmthickness of substantially 100 nm and a metal film 53 having a filmthickness of substantially 200 nm are sequentially deposited. The metalfilms 49 and 51 can be formed by sequentially depositing, for instance,a Mo film having a film thickness of substantially 0.1 μm, a Au filmhaving a film thickness of substantially 0.8 μm and a Mo film having afilm thickness of substantially 0.1 μm. The insulating films 50 and 52can be formed by depositing from bottom up a silicon oxide film, a SiNfilm and a silicon oxide film. The metal film 53 can be formed bydepositing a WSi film having a film thickness of, for instance,substantially 200 nm. In the embodiment 3, in a later process, fromthese metal film 49, insulating film 50, metal film 51, insulating film52 and the metal film 53, a capacitor element that has three-stages offirst through third stages of capacitor electrodes and a capacitorinsulating film made of the insulating film 50 or the insulating film 52between the respective electrodes is formed.

In the next place, as shown in FIG. 27, with a photoresist filmpatterned according to the photolithography technique as a mask, themetal film 53 is etched, thereby a third capacitor electrode 54 of acapacitor element that is formed in a later process is formed.

In the next place, as shown in FIG. 28, on the GaAs substrate 1, asilicon oxide film 55 having a film thickness of substantially 0.8 μm isdeposited and the third capacitor electrode 54 is covered with thesilicon oxide film 55. In place of the silicon oxide film 55, a SiN filmmay be used. Subsequently, according to the etching with a photoresistfilm patterned according to the photolithography technique as a mask,the silicon oxide film 55 and the insulating film 52 are patterned.Thereby, from the insulating film 52, a second capacitor insulating film56 of the capacitor element can be formed.

Subsequently, with the silicon oxide film 55 as a mask, the sputteringetching due to Ar ion is performed to pattern the metal film 51.Thereby, from the metal film 51, a second capacitor electrode 57 of thecapacitor element can be formed. FIG. 29 is a plan view showingpositional relationship between the third capacitor electrode 54, thesecond capacitor insulating film 56 and the second capacitor electrode57 when the second capacitor electrode 57 is formed, a cross sectionalong an A-A line in FIG. 29 corresponding to a cross section of thethird capacitor electrode 54, the second capacitor insulating film 56and the second capacitor electrode 57 in FIG. 28. In the embodiment 3,as shown in FIG. 29, the second capacitor electrode 57 (capacitorinsulating film 56) is planar and patterned so as to surround the thirdcapacitor electrode 54. At this time, the reason for the metal film 51being patterned by means of the sputter etching is because Au that formsthe metal film 51 is a material difficult to etch owing to a chemicalreaction. Furthermore, since the metal film 51 is patterned byphysically etching (sputter etching), Au and Mo that form the metal film51 that is ground by means of the sputter etching are splattered.However, during the patterning of the metal film 51, since the thirdcapacitor electrode 54 is covered with the silicon oxide film 55, the Auand Mo can be inhibited from causing inconveniences of adhering to thethird capacitor electrode 54. Thereby, the third capacitor electrode 54and the second capacitor electrode 57 can be inhibited from causinginconveniences of causing electrical short circuit.

In the next place, as shown in FIG. 30, on the GaAs substrate 1, asilicon oxide film 58 having a film thickness of substantially 0.8 μm isdeposited, and with the silicon oxide film 58 the silicon oxide film 55,the third capacitor electrode 54, the second capacitor insulating film56 and the second capacitor electrode 57 are covered. In place of thesilicon oxide film 58, a SiN film may be used. Subsequently, by means ofthe etching in which a photoresist film patterned according to thephotolithography technique is used as a mask, the silicon oxide film 55and the insulating film 50 are patterned. Thereby, from the insulatingfilm 50, a first capacitor insulating film 59 of the capacitor elementcan be formed.

Subsequently, with the silicon oxide film 58 as a mask, the sputteretching due to Ar ion is performed to pattern the metal film 49.Thereby, from the metal film 49, a first capacitor electrode 60 of thecapacitor element, a wiring (omitted from showing in the drawing) thatelectrically connects with the emitter electrode 37, a wiring 62 thatelectrically connects with the base electrode 38, a wiring 63 thatelectrically connects with the collector electrode 41 and a wiring 64that electrically connects with the resistance element 44 can be formed.According to the process up to here, a capacitor element C2 that is madeof the first capacitor electrode 60, the first capacitor insulating film59, the second capacitor electrode 57, the second capacitor insulatingfilm 56 and the third capacitor electrode 54 can be formed. FIG. 31 is aplan view showing positional relationship between the first capacitorelectrode 60, the first capacitor insulating film 59, the secondcapacitor electrode 57, the second capacitor insulating film 56 and thethird capacitor electrode 54 when the first capacitor electrode 60 isformed, a cross section along an A-A line in FIG. 31 corresponding to across section of the capacitor element C2 in FIG. 30. In the embodiment3, as shown in FIG. 31, the first capacitor electrode 60 (capacitorinsulating film 59) is planar and patterned so as to surround the secondcapacitor electrode 57. At this time, the reason for the metal film 49being patterned by means of the sputter etching is because Au that formsthe metal film 49 is, similarly to the metal film 51, a materialdifficult to etch owing to a chemical reaction. Furthermore, since themetal film 51 is patterned, similarly to the metal film 51, byphysically etching (sputter etching), Au and Mo that form the metal film49 that was ground by means of the sputter etching are splattered.However, during the patterning of the metal film 49, since the thirdcapacitor electrode 54 is covered with the silicon oxide film 55 and thesilicon oxide film 58 and the second capacitor electrode 57 is coveredwith the silicon oxide film 58, the Au and Mo can be inhibited fromcausing inconveniences of adhering to the third capacitor electrode 54and the second capacitor electrode 57. Thereby, the first capacitorelectrode 60 can be inhibited from causing inconveniences of causingelectrical short circuit with the second capacitor electrode 57 and thethird capacitor electrode 54.

In the embodiment 3, a case where the capacitor element C2 has threestages of capacitor electrodes (first capacitor electrode 60, secondcapacitor electrode 57 and third capacitor electrode 54) was explained;however, according to a similar process a capacitor element having fouror more stages of capacitor electrodes may be formed. Thus, in the caseof a capacitor element that has (n+1) (n is 2 or more) stages ofcapacitor electrodes being formed, firstly, metal films and insulatingfilms from which all of capacitor electrodes and capacitor insulatingfilms are formed are formed, and after the formation of these thin filmsaccording to a patterning method same as the patterning method with thesilicon oxide films 55 and 58 as masks, the thin films are patternedsequentially from top to down. Thereby, even in the case of a capacitorelement having (n+1) stages of capacitor electrodes being formed, theinconvenience that the respective capacitor electrodes cause electricalshort circuit therebetween can be inhibited.

Furthermore, as explained with FIGS. 29 and 31, since the firstcapacitor electrode 60 (first capacitor insulating film 59) is planarand patterned so as to surround the second capacitor electrode 57(second capacitor insulating film 56) and the second capacitor electrode57 (second capacitor insulating film 56) is planar and patterned so asto surround the third capacitor electrode 54, below the third capacitorelectrode 54 the second capacitor insulating film 57 can be inhibitedfrom being disposed at upper and lower portions of a sidewall of thesecond capacitor electrode 57 and below the second capacitor electrode57 the first capacitor insulating film 59 can be inhibited from beingdisposed at upper and lower portions of a sidewall of the firstcapacitor electrode 60. Thereby, it can be inhibited that the firstcapacitor insulating film 59 and the second capacitor insulating film 56bend, the first capacitor insulating film 59 and the second capacitorinsulating film 56 become locally thinner in the film thickness ordeteriorate in the film quality, and thereby the withstand voltage ofthe capacitor element C2 becomes lower. As a result, since the breakdownwithstand voltage of the capacitor element C2 can be improved, thecapacitance density of the capacitor element can be improved by thinninga film thickness of the capacitor insulating film. That is, according tothe embodiment 3, even in the case of a capacitor element having (n+1)stages of capacitor electrodes being formed, since the capacitorinsulating film can be inhibited from becoming locally thinner ordeteriorating in the film quality, the breakdown withstand voltage ofthe capacitor element can be improved.

Still furthermore, according to the forming method according to theembodiment 3 of a capacitor element, since the metal films that become(n+1) stages of capacitor electrodes and the capacitor insulating filmsdisposed between the respective metal films are sequentially deposited,density of foreign matters that come in between the metal films and thecapacitor insulating films can be reduced. Thereby, the deterioration ofthe capacitor withstand voltage caused by defects due to the foreignmatters can be inhibited from occurring.

In the next place, as shown in FIG. 32, on the GaAs substrate 1, a SiNfilm having a film thickness of substantially 0.5 μm and a silicon oxidefilm having a film thickness of substantially 0.5 μm are sequentiallydeposited to form an insulating film 65. Subsequently, with aphotoresist film patterned according to the photolithography techniqueas a mask, the insulating films 65, 45 and 43 are etched, and thereby anopening 66 that reaches the emitter electrode 37, openings 67 that reacheach of the wirings 62 through 64, an opening 68 that reaches the firstcapacitor electrode 60 in a region that is planar and where the secondcapacitor electrode 57 and the third capacitor electrode 54 are notdisposed, an opening 69 that reaches the second capacitor electrode 57in a region that is planar and where the third capacitor electrode 54 isnot disposed and an opening 70 that reaches the third capacitorelectrode 54 are formed. At this time, an opening area of the opening 70is formed so as to be larger than that of the openings 68 and 69.

Subsequently, on the insulating film 65 including the insides of theopenings 66 through 70, a Mo film having a film thickness ofsubstantially 0.2 μm and a Au film having a film thickness ofsubstantially 3 μm are sequentially deposited. Still subsequently,according to the etching in which a photoresist film patterned accordingto the photolithography technique is used as a mask, the Au film and theMo film are patterned to form a wiring 71 that electrically connectswith the emitter electrode 37, wirings 72 that electrically connect witheach of the wirings 62 through 64, a wiring 73 that electricallyconnects with the first capacitor electrode 60, a wiring 74 thatelectrically connects with the second capacitor electrode 57, and awiring 75 that electrically connects with the third capacitor electrode54 are formed. Here, FIG. 33 is a plan view of the capacitor element C2when the wirings 71 through 75 are formed, and a cross section along anA-A line in FIG. 33 corresponds to a cross section of the capacitorelement C2 in FIG. 32. As shown in FIG. 33, the opening 70 is formed soas to be planar and surrounded by the third capacitor electrode 54, andthe opening 69 is formed so as to be planar and surrounded by the secondcapacitor electrode 57. When the opening 70 is formed planar and at aposition deviated from the third capacitor electrode 54, there is fearin that owing to the wiring 75 disposed inside of the opening 70 thethird capacitor electrode 54 may be caused to short-circuit with thesecond capacitor electrode 57 and the first capacitor electrode 60, andwhen the opening 69 is formed planar and deviated from the secondcapacitor electrode 57, there is fear in that owing to the wiring 74disposed inside of the opening 69 the second capacitor electrode 57 andthe first capacitor electrode 60 may be caused to short circuit.However, when the opening 70 is formed so as to be planar and surroundedby the third capacitor electrode 54 and the opening 69 is formed so asto be planar and surrounded by the second capacitor electrode 57, suchinconveniences can be inhibited from occurring.

The present inventors studied means of forming a capacitor element C2according to a process in which, in forming a capacitor element C2, forinstance a first capacitor electrode 60 and wirings 61, 62 and 63 arepatterned beforehand; on the first capacitor electrode 60 and thewirings 61, 62 and 63 an interlayer insulating film is formed; after inthe interlayer insulating film an opening that reaches the firstcapacitor electrode 60 is formed, in the opening thereof a firstcapacitor insulating film 59 and a second capacitor electrode 57 areformed (including the patterning); further on the first capacitorinsulating film 59 and the second capacitor electrode 57 an interlayerinsulating film is formed; and after an opening that reaches the secondcapacitor electrode 57 is formed in the interlayer insulating film, inthe opening thereof the second capacitor insulating film 56 and thethird capacitor electrode 54 are formed (including the patterning). Inthe case of such means being used, in comparison with a manufacturingmethod of the capacitor element C2 according to the embodiment 3, aprocess of forming an opening for forming the first capacitor insulatingfilm 59 and the second capacitor electrode 57, a process of patterningthe first capacitor insulating film 59, a process of forming an openingfor forming the second capacitor insulating film 56 and the thirdcapacitor electrode 54 and a process of patterning the second capacitorinsulating film 56 are added. In this case, the capacitor element C2becomes a three-layered structure of wiring, a metal layer that issimultaneously formed with the second capacitor electrode 57 is usedalso as a second wiring, and a metal layer formed simultaneously withthe third capacitor electrode 54 is used also as a third wiring.Accordingly, normally, on the third wiring at the uppermost layer aprotective insulating film is formed and in the protective insulatingfilm an opening for forming a bonding-pad and so on is formed. On theother hand, according to the manufacturing method according to theembodiment 3 of the capacitor element C2, since the number of the wiringlayer may be two and these processes can be omitted, a manufacturingprocess of a semiconductor device can be simplified. Furthermore, informing a capacitor electrode having an n-stages of laminated capacitorinsulating film and (n+1) stages of capacitor electrode, even when n is3 or more, in comparison with an existing technique in which a (n+1)layered wiring layer is necessary, according to the embodiment 3, sincethe wiring layer can do with two layers, a process can be simplified.

In the next place, as shown in FIG. 34, after an insulating film 76 isdeposited on the GaAs substrate 1, an opening 77 that reaches wirings 71through 75 is formed. In the embodiment 3, as the insulating film 76, aSiN film or a laminated film in which a silicon oxide film and a SiNfilm are sequentially deposited can be illustrated. Thereafter, the GaAssubstrate 1 is cut by means of the dicing method or the like intoindividual chips, thereby semiconductor devices according to theembodiment 3 are manufactured.

In FIGS. 32 and 34 of the embodiment 3, the opening 68 that reaches thefirst capacitor electrode 60 is disposed to derive upward by use of thesecond wiring 73; however, the wiring 73 is not necessarily required.The first wiring simultaneously formed with the first capacitorelectrode 60 may be connected with the wiring 64 that connects with theresistance element 44 or the wiring 62 that connects with the baseelectrode 38. On the other hand, the opening 69 and the wiring 74 thatreach the second capacitor electrode 57 cannot be omitted because thesecond capacitor electrode 57 and the wiring 74 are electricallyconnected. When the procedure is repeated to form a capacitor elementhaving an n-stage laminated capacitor insulating film, even in the caseof n being 3 or more, according to the embodiment 3, a wiring layer cando with two layers.

FIG. 35 is a plan view of the chip. As shown in FIG. 35, on a chip CHP,other than the HBT, resistance element 44 and capacitor element C2 allaccording to the present embodiment, capacitor elements CM1, CM3 and CM4and inductors LM1 and LM3 are formed. Though omitted from showing in thedrawing, the capacitor elements CM1, CM3 and CM4 are formed according tothe process and in the shape same as that of the capacitor element C2.FIG. 36 is an essential plan view of a high-frequency power amplifierthat is formed by mounting the chip CHP shown in FIG. 35 on a wiringboard, FIG. 37 being an essential circuit diagram of the high-frequencypower amplifier. The high-frequency power amplifier is a transmissionpower amplification module (second module) PAM corresponding to, forinstance, a GMS (Global System for Mobile Communication) system of aworking frequency of substantially 800 to 900 MHz, a DCS (DigitalCellular System) system of a working frequency of substantially 1.8 to1.9 GHz or both of these. On a wiring board PLS that forms thetransmission power amplification module PAM, other than the chip CHP,capacitors CB1, CB2, CC1, CC2, CH1 and CH2 and inductors LC1, LC2, LH1and WB are mounted. The capacitors CB1, CB2, CC1, CC2, CH1, CH2, CH3 andCH4 and inductors LC1, LC2, LH1 and WB are individual chips that aredirectly assembled on the wiring board PLS according to, for instance, aface-down bonding method.

External electrode terminals in the transmission power amplificationmodule PAM are an RF-in as input terminal, an RF-out as output terminal,Vcc1 and Vcc2 as reference potential (power source potential) and Vbb1and Vbb2 as bias terminal.

Between the RF-in and the RF-out, two amplification stages are connectedin cascade. A first amplification stage and a second amplificationstage, respectively, are formed of a first circuit block CCB1 and asecond circuit block CCB2.

The RF-in is electrically connected through a predetermined inter-stagematching circuit to a base electrode of an HBTQ1 contained in the firstcircuit block CCB. The HBTQ1 amplifies a high-frequency power.Furthermore, the inter-stage matching circuit thereof is formed of thecapacitor element CM1 and the inductor LM1. An amplification system isconstituted into two stages; accordingly, a base electrode of an HBTQ2that is contained in the second circuit block CCB2 that is a secondamplification stage is connected through a predetermined inter-stagematching circuit to a collector electrode of the HBTQ1 in the formerstage. The inter-stage matching circuit disposed between the HBTQ1 andHBTQ2 is formed of the capacitor elements CM3 and CM4 and the inductorLM3.

Embodiment 4

In the embodiment 3, a case where the capacitors CB1, CB2, CC1, CC2,CH1, CH2, CH3 and CH4 (FIG. 36) are formed as chips that are directlyassembled to the wiring board PLS was illustrated; however, in thepresent embodiment 4, a case where the capacitors (passive elements)CB1, CB2, CC1, CC2, CH1, CH2, CH3 and CH4 are formed in one chip as anintegrated passive device (IPD) (first module) will be explained.

FIG. 38 is an essential sectional view of the integrated passive deviceand capacitors CH2, CH3 and CH4 are shown in particular. The capacitorsCH2, CH3 and CH4 are formed, on a GaAs substrate 1, according to aprocess same as the process that forms the capacitor element C explainedby use of FIGS. 4 through 13 in the embodiment 1. When the capacitorsCB1, CB2, CC1, CC2, CH1, CH2, CH3 and CH4 are thus formed in one chip asthe integrated passive device, in comparison with a case where thecapacitors CB1, CB2, CC1, CC2, CH1, CH2, CH3 and CH4 are respectivelyassembled as individual chips in the transmission power amplificationmodule PAM (FIG. 36), the capacitors can be assembled more compactly.Thereby, the transmission power amplification module PAM itself can bemade in a smaller size.

According to the above-mentioned embodiment 4 as well, an effect same asthe embodiment 1 can be obtained.

In the above, the invention achieved by the inventors was specificallyexplained based on the embodiments; however, it goes without saying thatthe present invention, without restricting to the above embodiments, canbe variously modified within a range that does not deviate from gist ofthe invention.

For instance, in the embodiment 1, a case where a FET is formed on aGaAs substrate was explained; however, in place of the GaAs substrate, asemi-insulating compound semiconductor substrate such as InP may beused. Furthermore, in the embodiment 4, an insulator substrate mainlymade of silicon oxide or aluminum oxide such as a quartz substrate or analumina substrate may be used. Since the quartz substrate and thealumina substrate are less expensive than GaAs and so on, amanufacturing cost of the IPD can be reduced. From a viewpoint ofhigh-frequency characteristics of a MIM (Metal Insulator Metal)capacitor, in comparison with a semiconductor substrate relatively highin the conductivity such as silicon, a semi-insulating compoundsubstrate is preferably used and an insulator substrate such as quartzis more preferably used.

A semiconductor device according to the present invention can be appliedto a high-frequency power amplifier such as a transmission poweramplification module.

1. A semiconductor device comprising: a capacitor element formed over asubstrate made of a semiconductor substrate or an insulator substrate,wherein the capacitor element comprises a lower electrode formed overthe substrate, a capacitor insulating film formed over the lowerelectrode and an upper electrode formed over the capacitor insulatingfilm; the lower electrode, the capacitor insulating film and the upperelectrode are formed flat over the substrate; and in a plane, an outerperiphery of the upper electrode is disposed more inside than an outerperiphery of the lower electrode.
 2. The semiconductor device accordingto claim 1, wherein the semiconductor substrate has GaAs or InP as amain component; and the insulator substrate has silicon oxide oraluminum oxide as a main component.
 3. The semiconductor deviceaccording to claim 2, comprising: a first module in which a plurality ofpassive elements is formed over the substrate, wherein the capacitorelement is included in the first module.
 4. The semiconductor deviceaccording to claim 3, wherein the first module is an integrated passivedevice.
 5. The semiconductor device according to claim 2, comprising: asecond module that operates at a frequency of 800 MHz or more, whereinthe capacitor element is included in the second module.
 6. Thesemiconductor device according to claim 5, wherein the second module isa power amplifier having a plurality of stages of circuit operating at afrequency of 800 MHz or more; and the capacitor element forms aninter-stage matching circuit between the circuits.
 7. The semiconductordevice according to claim 1, wherein in a plane the outer periphery ofthe capacitor insulating film is disposed at a position same as an outerperiphery of the lower electrode or more inside than the outer peripheryof the lower electrode.